SpaceCloud® computer solution for space systems with AMD HPC ROCm support.

iX10-100 SpaceCloud® solution

The iX10-100 is Unibap’s next-generation SpaceCloud® solutions that are compatible with AMD’s high performance library (HPC) called ROCm. The iX10-100 is based on the 14 nm AMD Ryzen V1000 family and offers up to 8 processor threads and up to 8 CU graphics acceleration along with PCIexpress generation 3.

Unibap is currently developing the iX10-100 with the support of the Space Agency and intends to have a lab version (EM) in the middle of 2020 and aviation hardware towards the end of 2020.


Illustration of iX10-100 (under development).

In addition to the 14 nm AMD processor technology, the iX10-100 has a default FPGA from Microsemi’s PolarFire family. The possibility of data storage is extended from the iX5100 with a shared M.2 slot that can either be SATA or NVMe (PCIe) based, with up to x4 lane generation 3. The number of available LVDS signals has been increased from 16 to 20.

The iX10-100 supports a long line of I / O, which can be further expanded through the FPGA. Support includes:

  • Gigabit Ethernet
  • LVDS (x30)
  • RS422/485
  • I2C
  • SPI
  • GPIO
  • USB v2
  • USB v3
  • SATA
  • mini-PCIe
  • JTAG


Optional I/O expansion on I/O board,

  • PCIexpress gen. 2, x4 lanes
  • SerDes
  • Camera Link
  • SpaceWire
  • SpaceFibre
  • CAN 2.0b


Indicative performance for iX10-100:

  • CoreMark v1.0, 25,506.95 (GCC9.2.1 20191102 -O3 -funroll-loops -fgcse-sm -mfpmath=both -DPERFORMANCE_RUN=1 -lrt / Heap)
  • Linpack, 54 GFLOPS
  • CLpeak, 2000 GFLOPS (fp16)
  • FPGA has 924 DSP block (18×18)
  • AMD-FPGA PCIe interconnect, x4 lanes gen 3 (12.8 GT/s)


Run Nvidia CUDA code on SpaceCloud®. Save development time Caffe TensorFlow Theano PlaidML MIOpen NCCL HIP

Unibap has adapted AMD’s high performance computing package (HPC), ROCm to the SpaceCloud® product family iX10 and newer.

Note. note that it is not possible to use the basic version of ROCm. Only the Unibap-adapted ROCm for SpaceCloud® can be used.

An example of converting Nvidia CUDA code with AMD HIP compiler for execution on the iX10 family.

$ hipify-perl square.cu > square.cpp // ROCmHipifyan Nivida CUDA code to generic cpp code.
$ hipcc square.cpp -o square_hip // Compile the cpp code with AMD “hip compiler” to either AMD or back to Nvidia.
$ ./square_hip // and finally run it on Unibap’s SpaceCloud® ROCm stack for AMD APU devices.

info: running Square CUDA example on device AMD Ryzen Embedded V1605B with Radeon Vega GFX
info: allocate host mem ( 7.63 MB) info: allocate device mem ( 7.63 MB)
info: copy Host2Device info: launch ‘vector_square’ kernel info: copy Device2Host
info: check result PASSED!